Integrated circuits are widely used in consumer, commercial and military applications. As is well known to those having skill in the art, an integrated circuit generally includes a semiconductor die which is potted with a potting material.
More specifically, a plurality of integrated circuits are generally formed on a semiconductor wafer using diffusion, epitaxial growth, ion implantation, deposition, photolithography and many other conventional processes, to fabricate a plurality of microelectronic devices in a microelectronic substrate. A plurality of patterned conductive interconnect (wiring) layers of conductive lines are fabricated on the microelectronic substrate, separated by insulating layers. The conductive layers are generally polysilicon, metal or alloys thereof and the insulating layers are generally silicon dioxide, silicon nitride or other insulating layers.
The wafer is then diced into chips, also referred to as semiconductor dies. The dies are then fixed onto lead frames and wire bonded to produce electrical connections between bonding pads on the die and the leads in the lead frame.
Then, the die and lead frame are potted with a potting material such as a potting compound resin. The potting material protects the semiconductor die from external effects, such as moisture and mechanical shock. The potting material may also help to transfer heat from the semiconductor die, and also electrically insulates the semiconductor die. To perform these functions, the potting compound resins generally have a relatively high permittivity.
Unfortunately, the potting material which covers the semiconductor chip or die may produce a parasitic capacitance between the patterned conductive interconnect lines. For example, when a potting compound such as plastic, ceramic or other resins is formed on the semiconductor die, and penetrates between the conductive regions such as metal lines in the outer layer of the integrated circuit, the potting compound may increase the parasitic capacitance.
As the integration density and the length of the conductive lines in an integrated circuit increase, this increase in parasitic capacitance may produce problems. For example, the performance of the drivers which drive the conductive lines may deteriorate, and the overall operation of the integrated circuit may degrade because the drivers have to drive larger parasitic capacitance than expected.
One technique for solving these problems is described in a publication by Luu T. Nguyen et al. entitled "Effects of Die Coatings, Mold Compounds, and Test Conditions on Temperature Cycling Failures", IEEE Transactions on Components, Packaging and Manufacturing Technology, Part A, Vol. 18, No. 1, March 1995, pp. 15-22. In this publication, an additional protective layer is coated on the integrated circuit, between the patterned conductive interconnect layers and the potting compound. However, the need to form an additional protective layer may increase the cost of the integrated circuit.